Create a VHDL file

From Fpga4u

Jump to: navigation, search

In this section, you will learn to create a project using VHDL instead of drawing all the schematics.

  1. Create a new VHDL file: File-> New, VHDL File
  2. Newvhdl.jpg

  3. Save the file
  4. Write the VHDL code corresponing to the multplier (you will need an entity with the proper inputs and outputs and an architecture with the correct behaviour)
  5. Save and compile, correct the possible errors (double-clicking on the error messages will direct you to the errors)

  6. Compile.jpg

Next: Simulation
or go directly to the
Pin assignment

Links - For more information on the Quartus II synthesis tool - Syntax Reference

Personal tools