Simulation in ModelSim

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ModelSim is a well known HDL simulator. ModelSim can be launched directly from Quartus if you have installed it. To install ModelSim see Install ModelSim.

Setting ModelSim installation path

To be able to run ModelSim, Quartus needs to know it's path. Choose Tools->Options. In the Option dialog window go in General / EDA Tool Options. You will see a list of software names. Enter the installation path for ModelSim-Altera.

Using ModelSim-Altera with a Quartus Project

Open your tutorial project, and choose Assignments->EDA Tool Settings and select Simulation in the left panel. In the Tool names List select ModelSim-Altera. In the options below you can choose to simulate directly the top level entity of your design or to run it from a testbench file. We will talk about this last option later, for now let the options unchanged and return to your project.

ModelSim cannot manage bdf files. If you have schematic files replace them with VHDL files. Remember you can generate vhdl from a bdf by opening the bdf file and going in Files->Create / Update->Create HDL Design File for Current File.

Simulation input vector with a script

Compile your project and run the ModelSim RTL Simulation by selecting Tools->EDA Simulation Tool->Run EDA RTL Simulation. ModelSim should pop-up and you should see a Library tab in the Workspace panel on the left. Expand the work library and double-click on the entity you want to simulate. It will run the simulation. Now select the desired signal in the Object panel, right click and choose Add to Wave->Selected Signals. You can add other signals by drag and drop it in the wave panel.

Now we can assert values for input signals. For that we will use the force command.


> force A 01 0ns
> force B 11 0ns, 10 100ns

We can now run the simulation for 200ns:

> run 200ns

Now you should see the simulation results in the wave panel.

Simulation input vector with a testbench

You can assert values to your design inputs with another vhdl file encapsulating it:

library ieee;
use ieee.std_logic_1164.all;

entity tb_mult is end;

architecture bench of tb_mult is
 signal a, b : std_logic_vector(1 downto 0);
 signal z : std_logic_vector(3 downto 0);

 component mult is
  port(a, b : in  std_logic_vector(1 downto 0);
       z    : out std_logic_vector(3 downto 0));
 end component;


 mult_0: mult port map(a=>a, b=>b, z=>z);

  wait for 100 ns;

  wait; -- process will be executed only once
 end process;
end bench;

Gate Level Simulation

Quartus generates a structural description of your design in your simulation folder. It can be used to do a gate level simulation with delay definition. Note that as opposed to RTL simulation, your project can contain bdf files. This is due to the fact that the only file used by modelsim is the VHDL one generated by Quartus.

The generated vhdl uses some components of altera's libraries. If you use ModelSim-Altera it will works directly, but if you have the original ModelSim software, you will have to import the altera's libraries. See the Quartus documentation for more details.

Compile your project and run the ModelSim Gate-Level Simulation by selecting Tools->EDA Simulation Tool->Run EDA Gate-Level Simulation. In ModelSim we have to load the delay definition file. Select Simulate->Start Simulation..., go in the SDF tab and add the .sdo file generate by Quartus. Go back in the Design tab, expand the work library, select the top level entity or, if you have one, your testbench and click OK.

Next steps are similar to RTL simulation.

Next: Pin assignment
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