Canevas Modules
From Fpga4u
Contents
Module Name
To do
Author:
©
This file is free to be copied and used by anyone
No guarantee is provide to its reliability
Behavior
Register's mapping
|
Avalon Model
- Use the Native Avalon slave implementation (Register mode)
- 0 wait in write access
- 1 wait in read access
Access to registers
As the access is done in Native mode, the :
- IORD()
- IOWR()
macro needs to be used in NIOS IDE. This was the preferred model until version 7.2 of Quartus/SOPC Builder.
If the design is implemented in Dynamic access, the IORD8(), IORD16() or IORD32() have to be used for reading and IOWR8(), IOWR16() or IOWR32() for writing. This access is recommended from version 8.0 of Quartus/SOPC Builder.
VHDL code
- xxx.vhdl to download.
- xxx library element (.zip) to download and save in your library element after unzipped.
