VHDL modules
From Fpga4u
This page is to be used for link on useful VHDL module, documentation, code and how to use them. (Canevas Modules)
Contents
Avalon and SOPC Builder
When they use the Avalon bus, they need to be integrated with SOPC Builder software from Altera. It is quite easy to implement a full embedded system based on a processor (as NIOSII) and specific programmable interface. SOPC Builder is a tool how automatically generate all the Avalon bus module from the information provided by the modules themselves and the Avalon rules.
The module generated by SOPC Builder is then used on QuartusII to create the FPGA system by adding external components and pins connections.
Programmable interfaces
Programmables interfaces are modules using the Avalon bus Memory Mapped interface and/or Streaming interface. They can be Avalon slave (AS) or Avalon Master/Avalon Slave (AM).
- Référence from Altera: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf
Parallel Port PIOSCN(AS)
Author: R.Beuchat, EPFL/IC/LAP & HESSO/hepia/LSN
© 2008
This file is free to be copied and used by anyone
No guarantee is provide to its reliability
Behavior
Avalon Slave module for a programmable Parallel Port, where each bit of the 8 bits port can be specified as:
- Input or Output with a Data direction Register, '0' --> Input (default at Reset), '1' --> Output
- A Write access to data register provide the value to Output if the direction is Output, in all case the value is memorized,and if the port was specified as input then output when the write was done, a change to the direction will output the last memorized value.
- A register where each bit write as '1' will provide a '1' in output bit, a '0' does not change the value. Function Set.
- A register where each bit write as '1' will provide a '0' in output bit, a '0' does not change the value. Function Clear.
- A register where each bit write as '1' will toggle (invert) the output bit. Function Not.
- The state at the pin level can be read.
- The memorized output value can be read.
Register's mapping
- Avalon slave bus programmable interface
- PIO parallel Port with Set, Clear and Not functions
- Direction of each bit programmable in the Direction register
- 0: Input (reset initialisation)
- 1: Output
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In reading the address 0, the interface provide alway the internal value of the register, even if the port is in Output.
In reading, the read back value is the written value
In reading address 1, 2, 3, we always read the external port value, thus if we don not have short circuit, we read the written valu in output mode, and the external input in input mode
The direction register has to be initialized before use of the port if we need output utilisation Writing a '1' to the corresponding bit put it in OUTPUT direction, a '0' in INPUT
Register at address 5, 6, 7 are for future use.
Avalon Model
- Avalon used with generic width (8 by default)
- Use the Native Avalon slave implementation (Register mode)
- 0 wait in write access
- 1 wait in read access
Access to registers
As the access is done in Native mode, the :
- IORD()
- IOWR()
macro needs to be used in NIOS IDE. This was the preferred model until version 7.2 of Quartus/SOPC Builder.
If the design is implemented in Dynamic access, the IORD8(), IORD16() or IORD32() have to be used for reading and IOWR8(), IOWR16() or IOWR32() for writing. This access is recommended from version 8.0 of Quartus/SOPC Builder.
VHDL code
- PIOSCN.vhdl to download.
- PIOSCN library element (.zip) to download and save in your library element after unzipped.
You have to unzip the PIOSCN.zip in a directory in your Altera Quartus own library directory.
This directory needs to be available to Quartus II and specifically SOPC Builder
(Tools --> Options --> IP Search Path, Add if necessary the Path library).
C code example
i2c (AS)
To do
Author:
This file is free to be copied and used by anyone
No guarantee is provide to its reliability
Behavior
Register's mapping
Avalon Model
Access to registers
VHDL code
- i2c library element (.zip) to download and save in your library element after unzipped.
Ethernet interface (AS)
To do
FX2 interface (AS)
To do
VHDL code
- fx2 library element (.zip) to download and save in your library element after unzipped.
PWM (AS)
To do
LCD controller (AM)
HITACHI TX07D09VM1CAB with touch screen [HITACHI LCD.zip]
Camera interface (AM)
- MT9V032 controller [MT9V032.zip]
- http://fpga4u.epfl.ch/wiki/FPGA4U_camera_modules_MT9V032
Extension instructions
Extension instructions are instruction to be added has NIOSII added instructions to the processor core.
Independent modules
VHDL code without NIOSII, Avalon bus connection. Useful code or demonstration.
SDRAM Controller
Basic SDRAM controller with a pipelined Avalon interface. Frequency is fixed at 120MHz. Adapt counter values if you change the frequency as speciefied in the SDRAM datasheet. Media:Fpga4u_sdram_controller.vhd Media:Fpga4u_sdram_controller_hw.tcl
