Connector for FPGA4U connexion

64 pins connector to FPGA4U

The FPGA4U bottom (male) connector is connected to the FPGARM4U top connector(female).

64 pins extension connector

ARM controller connections

Extension connections

• Extension Bus Interface 1 (EBI1) with:
  • A[22..0] Byte address
  • D[15..0] 16 bits data bus, tri-state bus, bidirectionnal,
    • Write direction: From ARM to FPGA
    • Read direction: From FPGA to ARM
  • nCS0 One Mapped area of 8MBytes, start ARM adddress: 0x7000 0000
  • nCS2 One Mapped area of 8MBytes, start ARM adddress: 0x9000 0000
    • nRD, select read access on D[15..0]
    • nWR0, select Write access on D[7..0]
    • nWR1, select write access on [D15..D8]
      • or
    • nRD, select read access
    • nWR, select write acces
    • nBS0, select access on D[7..0] (read or write)
    • nBS1, select access on [D15..D8](read or write)
    • A0 not available (nBS0 use the same pin)

• • nWAIT, from FPGA to ARM to insert wait state cycles for the current access
• Interruptions
  • FPGA4U-IRQ, to send an interrupt from FPGA to ARM
• DMA
  • FPGA4U-DMA, to send a request to the RAM for DMA transfers
• Clock
  • PCK0, clock from ARM4U board to FPGA
    • To PLL through CLK_from_bottom (FPGA PIN_M22)
    • To global input Clock pin DPCLK0 (FPGA PIN_J1)
• Reset, it's possible to Reset the ARM board from FPGA4U
  • nReset connected to SWITCH1[5] !!

Extension connections

• SPI interface, master or slave from SPI1 interface with 2 Slave select
  • SPI1_nPCS0
  • SPI1_nPCS1
  • SPI1_SPCK
  • SPI1_MOSI
  • SPI1_MISO
• Parallel Port PE, 2 free pins I/O
  • PE16
  • PE17

Connector assignment

Top connector on FPGARM4U, Bottom on FPGARM4U