Default Configuration
From Fpga4u
Every FPGA4U is configured with a small default application that shows the EPFL logo and displays FPGA4U onto the LEDs. It also includes several extra applications, such are the Game Of Life or the Snake.
Contents
FPGA4U
The source for the original FPGA4U configuration is available here. This design is relatively simple and made of hardware modules only.
FPGA4U DE0
The DE0 default design is richer than its predecessor, it includes a full system with a Nios II processor and a set of small applications.
Download
We made the sources available through a public SVN repository. You can checkout the sources by using the svn command
svn checkout https://svn.epfl.ch/svn/lap-fpga4u/trunk/config_DE0
Here is a small description of the content
- config_DEO: contains the quartus project files
- flash: contains a script to easily rewrite the default configuration.
- qsys_top: generated HDL sources describing the system
- software: the software project
Compiling the Quartus Project
The root folder contains the quartus project file. If you do not intent to change the hardware part of the design, you do not have to compile it as the repository provides the sof file, which is used to configure the FPGA. Otherwise you can simply open the project with Quartus, which will be ready to compile.
Compiling the Nios EDS Project
The software can be imported into your Nios II EDS workspace. The software consists in a pair of project, config_de0 contains the application sources, while config_de0_bsp provides a description of the hardware system and a set of device drivers. Both projects must be imported into your workspace.
Right-click in the Project Explorer pane and select Import... A window should pop up proposing you multiple types of imports. Select Nios 2 Build Tools Project > Import Nios 2 Build Tools Project. Browse to the first project location (config_DE0/software/config_de0) and specify a project name (e.g., config_de0). Click finish.
Repeat the operations for the config_de0_bsp project.
Before compiling you must regenerate the bsp of the config_de0_bsp project. In the Project Explorer, right click on the config_de0_bsp project and select Nios II > Generate BSP. Now you can compile the whole. In the Project Explorer, right click on the config_de0 project directory and select Build Project (Ctrl+B).
Programming the Board
Programming the design into the board is a two step operation.
First you should program the FPGA. This is only necessary if the hardware design is different from the one stored into the EPCS memory. In that case you can open the Quartus Programmer from the Nios II menu.
When the FPGA is configured with the correct design, you can load the software by right-clicking the config_de0 project and selecting Run As > Nios II Hardware.
If it fails make sure you program the correct hardware design. Otherwise, you may also want to check for connectivity. Go into the Run > Run configuration... menu. In the Target Connection tab, and press on Refresh Connections. Unchecking the boxes in the System ID checks may also help.
Programing the EPCS
In order to make your modification persistent, you need to program the EPCS. The EPCS is read during the initialization of the board and the FPGA gets programmed from its content.
To simplify the process, we created a script into the config_DE0/flash directory. To execute it, run the nios2-command-shell terminal. Go into the flash directory and type
./program_epcs.sh
It should generate some files to be loaded into the EPCS. Note that the script do not run any compilation, make sure that your hardware is compiled and that your software project is built.
If the programming fails, it may be because of a non-standard EPCS memory. Copy the file nios2-flash-override.txt from the flash directory to the nios2eds binaries (e.g., altera/{version}/nios2eds/bin), it will provide the missing information on the memory characteristics to the EPCS programmer.
