FPGARM4UDebugConfigure
From Fpga4u
Contents
OpenOCD Configuration
The configuration of OpenOCD is written in the file fpgarm4u.cfg.
To use this configuration script with OpenOCD, indicate these following path (either in a Windows shortcut or in Eclipse) :
- Target : PATH_INSTALLATION_OPENOCD\bin\openocd.exe -f fpgarm4u.cfg -l log.txt -c "reset init"
- Start in PATH_CONFIG_OPENOCD\fpgarm4u
The variable PATH_INSTALLATION_OPENOCD, PATH_CONFIG_OPENOCD depend on your installation paths.
Several parts have to be configured such as the OpenOCD daemon, the JTAG interface, the CPU, etc. The different configurations are explained below.
The reference documentation for OpenOCD can be found on its website.
The reference documentation for the Atmel board AT91SAM9263, which is the skeleton of the FPGARM4U board, can be found on Atmel's website.
Chip constant
The chip name used in this guide is at91sam9263. The target is the processor ARM, then the target name is at91sam9263.
There is also need to declare the ID of the CPU, this can be found in the doc of the at91sam9263 board. For the processor ARM 926EJ-S, the ID is 0x0792603F.
set _CHIPNAME at91sam9263 set _CPUTAPID 0x0792603F set _ENDIAN little
Daemon configuration
We need to define the ports of telnet and of the GDB. The default values are
- 3333 for GDB;
- 4444 for telnet.
Note that we are going to use the default values. The breakpoints are set to hardware instead of software, otherwise GDB doesn't always work correctly. The memory map is used to allow GDB to get the memory map so that it can know where things are. As the flash memory is not used, no need to enable the flash programming.
The debug level's range is from 0 to 3 (which writes to maximum of debug information).
telnet_port 4444 gdb_port 3333 gdb_detach resume gdb_breakpoint_override hard gdb_memory_map enable gdb_flash_program disable debug_level 3
Interface configuration
The interface hardware is the JTAG key tiny which can be found in the interface folder of OpenOCD. The configuration is already given.
To that, it is necessary to add the JTAG speed. It is 1/6 of the processor frequency, then at most 5.45 KHz if the processor runs at 32.768 KHz. The processor needs to be configured to run at 200 MHz, that will come later.
source [find interface/jtagkey-tiny.cfg] jtag_khz 5 # 5.45 kHz max
Reset configuration
The reset is important. There are two kind of resets : target and board. Here, both will be reset but the board will be reset first.
jtag_nsrst_delay 200 # ms jtag_ntrst_delay 200 # ms reset_config trst_and_srst srst_pulls_trst
TAP declaration
Each chip that OpenOCD will have to debug must have a TAP. Here, the only TAP is the CPU.
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
CPU declaration
At the previous section, the TAP of the CPU was added, but OpenOCD needs more pieces of information, such as the type of the processor, its endianess, etc. The physical area is the on-chip SRAM. It accelerates the data transfer.
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
$_TARGETNAME configure -work-area-virt 0x0 -work-area-phys 0x300000 -work-area-size 0x100000
$_TARGETNAME configure -event reset-init { ... include Reset-Init event operations here ... }
Reset-Init event
This section is executed when a reset/init event is fired. It is here that all the registers of the CPU can be configured.
The documentation used for this guide is the AT91SAM9263 Preliminary. The page numbers indicated below refer to this documentation.
Reset Controller User Interface
The activation of the user reset triggers a User Reset when a low level is detected on the pin NRST.
The external reset duration is approximately 150 us.
| Reset value | Required value |
|---|---|
| - | 0xA5000501 |
mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
See page 120 of the doc.
Watchdog Timer User Interface
The watchdog has to be disabled, otherwise it will reset the CPU every time that we are debugging it.
The register WDT_MR at address 0xfffffd44 is the Watchdog's Mode Register. Writing 1 in the bit #15 disable the watchdog.
| Reset value | Required value |
|---|---|
| 0x3fff2fff | 0x00008000 |
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
See page 140 of the doc.
Clock Generator
When the board is reset, the default clock is the slow clock (SLCK). To have the programs executed as fast as it is possible as well as a good speed for JTAG transfer, the processor should run at its maximum speed.
The interesting pages for this part are : page 28 (general schema bloc overview), chapter 27 (Clock Generator) and chapter 28 (Power Management).
The table below shows the frequencies of the different input clocks (output of oscillators) :
| Clock | Frequency |
|---|---|
| SLCK | 32.678 KHz |
| MAINCK | ~18.2 MHz |
The processor ARM 926EJ-S is able to run up to 200 MHz. To do so, five steps are required.
The first step is to enable the main oscillator which furnishs a clock of about 18.2 MHz instead of the 32.678 KHz of the slow clock. The register CKGR_MOR at address 0xFFFFFc20 is responsible for enabling the main oscillator.
| Reset value | Required value |
|---|---|
| 0x00000000 | 0x00004001 |
mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator after ~16 ms sleep 20 # wait 20 ms
The second step is to set the PLL A to the max frequency. The PLL uses a divider and a multiplier which allow the choose the frequency the most precisely using MAINCK as input clock. As it is difficult to have exactly 200 MHz, the frequency will be adapted to the nearest value that it is possible to have with the multiplication and the division : 198.656 MHz. The register CKGR_PLLAR at address 0xfffffc28 has to be written to change the PLL values.
| Reset value | Required value |
|---|---|
| 0x00003f00 | 0x2060bf09 |
mww 0xfffffc28 0x2060bf09 sleep 20
The third step is to switch from the slow clock oscillator to the main oscillator. The register PMC_MCKR at address 0xfffffc30 is responsible for choosing the master clock (switch between clocks (Slow Clock, Main Clock, PLLs)). Firstly, the Main Clock is chosen as Processor Clock divided by 2. Secondly, the PLL A is chosen as clock source.
| Reset value | Required value |
|---|---|
| 0x00000000 | 0x00000100 |
| Reset value | Required value |
|---|---|
| 0x00000100 | 0x00000102 |
mww 0xfffffc30 0x00000100 # MCK : PCK / 2 sleep 10 mww 0xfffffc30 0x00000102 # Clock from PLLA is selected sleep 10
The fourth step is to configure the PIO controller so that PCK may be output. It disables interruptions, pull ups, etc.
| Reset value | Required value |
|---|---|
| - | 0x00000000 |
| Reset value | Required value |
|---|---|
| - | 0x00000000 |
| Reset value | Required value |
|---|---|
| - | 0x00000000 |
| Reset value | Required value |
|---|---|
| - | 0x00000000 |
mww 0xfffff444 0xc0000000 # PIO_IDR : Interrupt disable mww 0xfffff460 0xc0000000 # PIO_PUDR : Pull Up disable mww 0xfffff470 0xc0000000 # PIO_ASR : Pull Up Status mww 0xfffff404 0xc0000000 # PIO_PDR : Controller PIO disable sleep 5
See page 434 of the doc.
Bus configuration
The Bus Matrix Slave Configuration Register is used, among others, to limit the maximum number of allowed cycles for a burst.
This limit has been placed to avoid locking a very slow slave when very long bursts are used.
| Reset value | Required value |
|---|---|
| 0x00000010 | 0x00000040 |
mww 0xffffec50 0x00000040
See page 157 of the doc.
Interface speed
Now that the speed of the processor has been up, it is possible to increase the speed of the JTAG. The rule of the 1/6 of the frequency processor is still there though.
jtag_khz 33000 # 33 MHz
SDRAM
To activate SDRAM, it is needed to configure some registers which will allow its use and to configure the SDRAM itself.
The SDRAM is connected to the External Bus 0.
The first register to configure is the Chip Select Assignment. This register enables the SDRAM Controller and specify at which voltage the memory is powered.
| Reset value | Required value |
|---|---|
| 0x00010000 | 0x00010002 |
mww 0xffffed20 0x00010002
See page 160 of the doc.
The 16 upper bits of the data pass through the PIO D. It is then needed to deactivate it.
| Reset value | Required value |
|---|---|
| - | 0x00000000 |
| Reset value | Required value |
|---|---|
| - | 0x00000000 |
| Reset value | Required value |
|---|---|
| - | 0x00000000 |
| Reset value | Required value |
|---|---|
| - | 0x00000000 |
mww 0xfffff844 0xffff0000 # PIO_IDR : Interrupt disable mww 0xfffff860 0xffff0000 # PIO_PUDR : Pull Up disable mww 0xfffff870 0xffff0000 # PIO_ASR : Pull Up Status mww 0xfffff804 0xffff0000 # PIO_PDR : Controller PIO disable
Then, the configuration of the SDRAM controller has to be set (e.g. number of column bits, data bus width, ...).
| Reset value | Required value |
|---|---|
| 0x852372C0 | 0x85227259 |
mww 0xffffe208 0x85227259 sleep 10
The memory type is also needed. There is the choice between SDRAM and Low-power SDRAM.
| Reset value | Required value |
|---|---|
| 0x00000000 | 0x00000000 |
mww 0xffffe224 0x00 sleep 1
In order to activate the SDRAM correctly, a precise protocol must be followed (see page 235 of the doc). The first part has already been executed. The second part is explained below. The register SDRAMC_MR is the Mode Register where all different states are written. The write operations are required by the protocol.
Issue a NOP command to the SDRAM.
mww 0xffffe200 0x01 mww 0x20000000 0
Issue an All Bank Precharge to the SDRAM.
mww 0xffffe200 0x02 mww 0x20000000 0 sleep 1
Eight auto-refresh (CBR) cycles are provided.
mww 0xffffe200 0x04 # 1st mww 0x20000004 1 mww 0xffffe200 0x04 # 2nd mww 0x20000008 2 mww 0xffffe200 0x04 # 3rd mww 0x2000000c 3 mww 0xffffe200 0x04 # 4th mww 0x20000010 4 mww 0xffffe200 0x04 # 5th mww 0x20000014 5 mww 0xffffe200 0x04 # 6th mww 0x20000018 6 mww 0xffffe200 0x04 # 7th mww 0x2000001c 7 mww 0xffffe200 0x04 # 8th mww 0x20000020 8
Issue a Mode Register Set (MRS) to program the parameters of the SDRAM.
mww 0xffffe200 0x03 mww 0x20000020 0x0
Write the refresh rate in the Refresh Timer Register. The refresh time is MCK * 7 / 1M with MCK = 100 MHz.
mww 0xffffe204 0x000002b8
Set the SDRAM Controller to normal mode.
mww 0xffffe200 0x00 mww 0x20000000 0
End of configuration
To terminate the configuration, OpenOCD will execute some commands.
init reset run sleep 500 halt
GDB
The configuration of GDB is simpler but also very important. It is written in the file fpgarm4u.gdb.
To use this configuration script with OpenOCD and Eclipse, indicate its path in Eclipse > Run > Run configurations ... > Debugger. The easiest way is to put it in the same directory as the configuration file of the FPGARM4U for OpenOCD (PATH_CONFIG_OPENOCD).
Open a connexion with OpenOCD on the port configured in the configuration of OpenOCD.
target remote localhost:3333
Soft reset of the target, then halt.
monitor soft_reset_halt
Load the program into SDRAM.
load
Go to the beginning of the SDRAM in order to run the program.
monitor reg pc 0x20000000
Make a step for synchronization.
stepi
Eclipse
The program available here interacts with a Bridge designed on the FPGA of the FPGA4U by accessing it several times. To do that, the External Bus Interface 1 and the Static Memory Controller are used.
