LCD Display TX06

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Introduction

The Hitachi TX06D57M0AAA is a 2.2" QVGA display module. (http://www.hitachi-displays-eu.com/doc/TX06D57VM0AAA.pdf)

It has a complex driver ICs that make it very configurable. A few features are listed here:

  • power saving features
  • OSD (On-Screen Display)
  • internal RAM for partial display
  • mirroring of the screen, both vertically and horizontally

Specification

  • Resolution: 240x320
  • Number of Colors: 262,144 (18-bit RGB)
  • Backlight: 4 LEDs

Interface

The display has two interfaces:

System Interface

SPI (Serial Peripheral Interface): This interface is used for the configuration of the display and reading/writing to internal RAM. This interface is shared with the SD/MMC Flash Card Reader.

External Display Interface

16-bit or 18-bit RGB interface. The RGB data is synced with 3 signals: dotclk, hsync and vsync. This interface behaves very much like the standard VGA interface, the main difference being that this one is clocked.

Backlight

The backlight of the display module is made up of 4 white LEDs. In order to attain the required voltage (12.8V) to drive the LEDs, a LED driver is included on the board. (National Semiconductor LM2707) To achieve different levels of brightness, one needs only apply a PWM (Pulse Width Modulation) to the enable pin of the LM2707.

Controller

The controller for the extension card is fully Avalon compatible and is provided as a SOPC Builder Component. It can simply be dragged into the system being created and connected to the NIOS II CPU and SDRAM.

NOTE: Because of the high bandwidth required to transfer data from SDRAM, you must assign to both master ports of the controller 8 shares to the SDRAM. This will guarantee that enough is reserved for the controller, as otherwise, the CPU would prevent the controller from doing its job.

The controller is divided into 2 parts:

  • graphics: displays images at 16 bits per pixel
  • text: displays ASCII text in 16 colors

Each part has its own datapath and its configuration registers. Both parts can be activated simultaneously and they merge together with various options.

Though the controller works for both the LCD display and a VGA monitor, they cannot switch on the fly. The decision must be made when the system on chip is synthesized. The problem is that the LCD display requires a clock of about 8MHz and VGA requires 25MHz. Since there is only one clock pin going to the extension circuit, the two possible clock outputs would need to be multiplexed, which breaks the timing and gives bad quality images. Just apply the desired clock to the controller input and setup the registers accordingly.

Register Map

Register Address Size Description
Control 0x00 8 bits Sets global settings for the controller
Status 0x01 8 bits Contains status flags of the controller
Start 0x02 8 bits Activates the display
Stop 0x03 8 bits Stops the display
GFXAddr 0x04 32 bits Memory Address of the image to display
GFXLen 0x06 24 bits Length in bytes of one row of the image
GFXCtrl 0x08 8 bits Sets settings for the graphics mode
TXTAddr 0x09 32 bits Address of character row table
TXTLen 0x0A 24 bits Length of a row of text (in number of bytes)
TXTCtrl 0x0B 8 bits Sets settings for the text mode
BLPeriod 0x10 16 bits LCD Backlight Period
BLDtyCycle 0x11 16 bits LCD Backlight Duty Cycle
HorPulse 0x20 16 bits Length of the horizontal sync pulse
HorStart 0x21 16 bits Beginning of horizontal active area of display
HorStop 0x22 16 bits End of horizontal active area of display
HorTotal 0x23 16 bits Total length of a row
VerPulse 0x24 16 bits Length of the vertical sync pulse
VerStart 0x25 16 bits Beginning of vertical active area of display
VerStop 0x26 16 bits End of vertical active area of display
VerTotal 0x27 16 bits Total number of rows in a frame
SyncCtrl 0x28 8 bits Sets configuration of sync signals


Control (0x00)
Bits 7 - 6 5 4 3-1 0
Reserved VIE HIE Reserved VGA
VIE: Vertical Interrupt Enable
HIE: Horizontal Interrupt Enable
VGA: (0: LCD, 1: VGA) At the moment, selection of video out mode must be selected at compile time of the System on Chip, by choosing the appropriate clock (25MHz for VGA and 10MHz for LCD). Set the VGA bit accordingly.
Activating the VIE and/or HIE will enable interrupts everytime a vertical blank, respectively a horizontal blank period is started. In order to acknowledge the interruption, write to the corresponding bit in the status register (0x01).
Status (0x01)
Bits 7 - 6 5 4 3 2 1 0
Reserved VI HI Reserved VB HB R
VI: Vertical Interrupt: Writing a '1' to this bit will acknowledge the interrupt
HI: Horizontal Interrupt: Writing a '1' to this bit will acknowledge the interrupt
VB: Vertical Blank: a '1' means the controller has entered the vertical blank period
HB: Horizontal Blank: a '1' means the controller has entered the horizontal blank period
R: Running: a '1' means the controller is running, i.e. a Start command has been sent (0x02). A Stop command (0x03) will set it to '0'.
This register can only be read. Writing only has an effect on bits 4 and 5.
Start (0x02)
Bits 7 - 0
Start
Start: Starts the controller
This register can only be written. Reading will return 0's. Writing anything to this register will start the display. Note: if using the LCD screen, it must have been previously configured via SPI.
Stop (0x3)
Bits 7 - 0
Stop
Stop: Stops the controller
This register can only be written. Reading will return 0's. Writing anything to this register will stop the display.
GFXAddr1 (0x04)
Bits 31 - 0
Address
Address: Address of the image to display
Write into this register the address of the frame to be displayed.
GFXLen (0x06)
Bits 23 - 0
Length
Length: Length of one row of the image to display in bytes
This register must contain the length of one row of the image since the controller grabs one line at a time. It is assumed that the rows are placed one after the other in memory and that there are as many rows as needed to fill the entire screen.
GFXCtrl (0x08)
Bits 7 - 1 0
Reserved GON
GON: 0: Graphics off, 1: Graphics on
This register contains the controls for the graphics part of the controller. At the moment it only contains the bit to turn graphics on or off. When graphics are turned off, the controller will simply stay idle and not fetch anything from memory. Text mode will still work however.
TXTAddr (0x09)
Bits 31 - 0
Address
Address: Address of the the text table
This register holds the address of the text table. The text table is a table containing pointers to rows of text. Text is handled on a row by row basis. At the beginning of each row of text, the controller checks in this table to find the pointer to the corresponding row of text. The length of the text table is the number of rows of text (30 in the case of 16x8 text in 640x480).
TXTLen (0x0A)
Bits 23 - 0
Length
Length: Length of a text line
This register contains the length of one row of text, as a number of bytes. One character takes 2 bytes, so this contains 2 times the character width of the screen. (160 = 2 * 80, with 80 being the number of columns of text in 640x480 mode)
TXTCtrl (0x0B)
Bits 7 - 4 3 2 1 0
LIN FGT BGT Reserved TON
LIN: Number of lines in one character (0 means 16 lines). Default is 16 and this should only be changed if there is a change in the ascii characters.
FGT: Foreground transparency. When this bit is activated, the foreground of text will be transparent and will show the graphics underneath. This only works when graphics mode is also enabled.
BGT: Background transparency. When this bit is activated, the background of text will be transparent and will show the graphics underneath. This only works when graphics mode is also enabled.
TON: 0: Text off, 1: Text on
This register contains the control bits of the text mode. If TON is not set, then the text part of the controller is idle, and there is no text being displayed. It will not fetch anything in memory. The graphics part of the controller may still be on.
BLPeriod (0x10)
Bits 15 - 0
Period
Period: Period of the PWM for the backlight of the LCD panel.
The brightness of the backlight of the LCD display is regulated by applying a PWM (Pulse-Width Modulation) to its input pin. Use this register to set the period of the PWM.
BLDtyCyc (0x11)
Bits 15 - 0
Duty Cycle
Duty Cycle: Duty cycle of the PWM for the backlight of the LCD panel.
This register defines the duty cycle of the PWM for the LCD backlight. If this register contains a value bigger or equal to BLPeriod, then the backlight will be at 100% brightness. If it is 0, the backlight will be off.
Sync (0x20 - 0x27)
VGA Timing Diagram
Bits 15 - 0
(0x20) HorPulse
(0x21) HorStart
(0x22) HorStop
(0x23) HorTotal
(0x24) VerPulse
(0x25) VerStart
(0x26) VerStop
(0x27) VerTotal
HorPulse: Length of the horizontal sync pulse
HorStart: Beginning clock of the active display area
HorStop: End clock of the active display area
HorTotal: Total clocks of a row
VerPulse: Length of the vertical sync pulse
VerStart: Beginning row of the active display area
VerStop: End row of the active display area
VerTotal: Total rows of a frame
The sync timings are described in the diagram on the right.
SyncCtrl (0x28)
Bits 7 - 2 1 0
Reserved VP HP
VP: Polarity of the vertical sync signal
HP: Polarity of the horizontal sync signal
When polarity is set to '0', then the signal is active low, and when it is set to '1' it is active high.

Drivers and libraries

There are several sets of drivers and libraries provided for the extension card. They are written in C to be used with the NIOS II softcore processor.

  • The driver for the LCD/VGA Controller, with basic library for functions and procedures to display images and text on screen.
  • The low-level SD driver and library which implements basic read/write functions for SD cards (MMC cards not yet supported).
  • FAT16 filesystem library used over SD driver. Basic functions only, needs to be extended.

Files

  • SOPC Builder component: (extlcd_ctrl.zip): This file contains the component that needs to be added to the SOPC Builder system. Make sure that this folder is in a path that SOPC Builder looks into.
  • Drivers and Libraries: (extlcd_software.zip): These files are to be added to your NIOS II project. They provide the necessary drivers to run the device.
  • Pin Assignment file: (extlcd_pin_assignment.xls): This file contains the pin assignment for the extension. !! Version A of the board, uncompatible with versions B/C !!
  • Pin Assignment file: (_pin_assign_FPGA4U_ExtLCD_B.tcl): This file contains the pin assignment for the extension, version B and C
  • A simple Quartus bdf for pin assignement TstLCD.bdf

Links

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